An integrated circuit (IC) includes a large number of tiny transistors on a small chip. An integrated circuit may contain a memory device, where information is stored in the form of binary data. Memory devices can be fabricated such that the data is volatile or nonvolatile. A nonvolatile memory device, e.g., read only memory (ROM), retains its stored information even if it loses power. ROM devices are designed to output pre-coded information. The pre-coded information is specifically designed into the memory device array section during manufacturing; this defines the state of each ROM. Once the manufacturing process is complete, the pre-coded information becomes a permanent part of the memory device.
In contrast, a volatile memory device, e.g., random access memory (RAM), loses its stored information when it loses power. Unlike ROM devices, the state of each RAM device is initially unknown when the manufacturing process has been completed; and once initialized, the state is only retained while the device is powered.
FIG. 1 illustrates an example of a RAM device, i.e. a static RAM device, which loses its initial state when it loses power. The SRAM device 50 comprises an array 58 comprising a plurality of SRAM cells 10 (FIG. 2). As shown in FIG. 2, a data bit is stored in the SRAM cell 10 on four transistors 12, 14, 16, and 18 that form a latch comprising two cross-coupled inverters. Two control transistors 20 and 24 control access to SRAM cell 10 during read and write operations. Data is stored with either a high potential at a bit data node A and a low potential at a bit data node B, or a low potential at the bit data node A and a high potential at the bit data node B. Hence, two stable states are available which are arbitrarily defined as a logic ‘1’ or a logic ‘0’.
The logic state of SRAM cell 10, i.e., either a ‘1’ or ‘0’, is read by sensing the cell current on bit line pair comprised of bit line output 26 and bit line input 28 and/or the differential voltage developed there between. When word line input 30 and word line output 21 are selected, SRAM cell 10 is activated by turning on control transistors 20 and 24. If the activated SRAM cell 10 is in logic state ‘1’, node A is high and node B is low. Transistor 14 will be off, transistor 18 will be on, transistor 12 will be on, and transistor 16 will be off. Since transistors 18 and 24 are on, bit line input 28 will carry cell current, while bit line output 26 will not carry any cell current. A stored logic state ‘0’ would include having node A low and node B high. Transistor 14 will be on, transistor 18 will be off, transistor 12 will be off, and transistor 16 will be on. Bit line output 26 will carry cell current, while bit line input 28 will not carry cell current.
Referring to FIG. 1, 2N×2M bits are arranged in the array 58 with 2M columns and 2N rows. To read data stored in the array 58, a row address is input and decoded by row decoder 52 to select one word line input 30 and one word line output 21. All of the SRAM cells 10 along word lines 30 and 21 are activated. Column decoder 54 addresses one bit out of the 2M bits that have been activated and routes the data that is stored in that bit to a sense amplifier (not shown) and then out of the array 58. Data in and Data out are controlled by the Read/Write Control circuit 56.
There are variations of RAM devices where the state of the memory device is not lost when it loses power, e.g., nonvolatile RAM (NVRAM) and shadowed memories. An NVRAM's initial state is defined after the manufacturing process has been completed, and typically, the state at power-up is the same as the final state before the previous power-down. Shadowed memories usually contain a RAM portion and an NVRAM portion. As previously mentioned, the initial state of an NVRAM device is set after the manufacturing process, and in shadowed memories, the initial state of the RAM at power-up is obtained by copying the NVRAM stored contents into the RAM. At anytime, it is possible to perform a special sequence to erase the NVRAM and reprogram it to hold the same data as stored in the RAM. In some applications it would be beneficial to have the initial state of volatile memory devices, such as e.g., a static RAM (SRAM), set during manufacturing. It is also beneficial to prevent the stored contents or the current state from being lost when the volatile memory device loses power.
The cost of designing and developing an individual complex integrated circuit can be very costly because an IC comprises millions of interconnected devices. However, ICs are produced as a unit using common photolithography and other fabrication processes, and millions of production units can be mass produced; thereby substantially minimizing individual IC costs. Typically, for a particular fabrication technology, the cost of the IC is proportional to its area; therefore, techniques for reducing an IC's area size are beneficial because they will also reduce costs.
The IC fabrication process involves several steps that require an optically precise image of a stage of the IC being fabricated; the image is generally referred to as the mask. The complete fabrication process may require numerous masks, and a complete set of masks are very expensive.
After the fabrication of a set of masks is complete, any design changes to the IC being fabricated, due to a design error or a desire to produce a part tailored to a specific application, can be very expensive because corresponding changes must be made to the set of masks. The mask for each stage in the fabrication process has a different cost associated with the precision and complexity associated with its manufacture. Therefore, it would be beneficial to make design changes to a restricted number of masks. With respect to ROM devices, it is beneficial to design the memory device such that its contents can be modified by changing a limited number of the lower-cost masks.